Fractile is a UK AI hardware startup building next-generation inference chips and systems for frontier AI.
<p><span style="font-size: 12pt;"><strong>Verification Engineer</strong></span></p> <p><strong>About Fractile</strong></p> <p>Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.</p> <p>The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.</p> <p> </p> <p><strong>Our ideal candidate could have 3+ years’ experience. This is a unique opportunity to accelerate your development, working with an experienced and collaborative team and gaining exposure to a broad range of disciplines. At Fractile, we value ideas from everyone, regardless of title or tenure, and we believe the best engineering happens when people share, question, and learn together. You’ll be joining a culture where your curiosity is encouraged, your input matters, and there’s real room to grow.</strong></p> <p>As a Silicon Verification Engineer, you will be based in either our Bristol or London office in the UK. We are looking for you to take an active role in building world-class ML/AI IC products for scale-out to data centre applications. We are looking for someone who is passionate about verification – not someone content to go through the motions, but rather looking to push the field further forwards. If you get excited about bringing software concepts to hardware workflows, and enjoy improving established practices to increase tape-out quality and bring down costs, then this is the role for you.</p> <p>You’ll work closely with colleagues across modelling, system architecture, and RTL design to ensure our RTL releases meet the highest standards of functional quality. That includes contributing to discussions around specification, architecture, and the workflows that connect them. Your work will be integral to delivering our highly disruptive and ambitious product.</p> <p><strong>We look for engineers with the following mindset:</strong></p> <ul> <li>Software mindset for solving hardware problems</li> <li>The desire to be in a high impact role in a small team</li> <li>A disrupter of the “status quo” of hardware development</li> <li>Eagerness to contribute to and improve working practices and help build connections between hardware and software teams</li> <li>Detail-focused, with rigour as the baseline for all work</li> <li>Humility, desire to learn</li> <li>Happy to be part of a fast-paced, open and collaborative environment</li> </ul> <p><strong>Required skills and experience:</strong></p> <ul> <li>Strong software skills <ul> <li>Python (or another object oriented language e.g C++)</li> </ul> </li> <li>Understanding of digital hardware concepts <ul> <li>Ability to read and debug RTL in SystemVerilog</li> <li>Familiarity with debugging waveforms</li> </ul> </li> </ul> <p><em><span class="notion-enable-hover" data-token-index="0">Candidates with a UVM or a strong software background are encouraged to apply even without an RTL background</span></em></p> <p><strong>Desirable skills and experience:</strong></p> <ul> <li>Pre-silicon RTL verification <ul> <li>Verification planning and execution from specification</li> <li>Building testbenches</li> <li>Stimulus creation</li> <li>Functional modelling of hardware blocks</li> <li>Checker creation</li> <li>Coverage definition/closure</li> </ul> </li> <li>Transaction-Level Modelling <ul> <li>Whether in UVM, SystemC or another methodology</li> </ul> </li> <li>SystemVerilog Assertions (SVA)</li> <li>Software fluency in multiple languages</li> <li>Open source tools for silicon development <ul> <li>Cocotb (used for all our testbench collateral), Verilator, Icarus Verilog</li> </ul> </li> <li>Commercial EDA tools</li> <li>Formal verification</li> <li>Working in a monorepo environment alongside software <ul> <li>Bazel is our chosen tool, familiarity is not expected</li> </ul> </li> <li>Contributing to architecture discussions</li> </ul> <p><strong>How we work</strong></p> <ul> <li>Ownership and execution: you will have full agency to drive your work forward</li> <li>Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines</li> <li>Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact</li> <li>Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there</li> <li>Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is</li> </ul> <p style="text-align: left;"><strong><em>What We Offer</em></strong></p> <ul> <li>Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role.</li> <li>Equity & Ownership: meaningful equity so everyone shares in the value creation.</li> <li>Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.</li> <li>Diverse & fun office: we believe the hardest prob