Claros is a power management solutions company developing hardware and software to improve efficiency, resilience, and sustainability of data center power delivery.
<div class="content-intro"><p>Claros is a power management solutions company that is innovating at the intersection of power and compute to make AI more sustainable and widely available. By driving down the cost and complexity of power delivery and leveraging innovative hardware and software, the company seeks to decrease energy consumption, optimize power delivery, increase compute performance, and maximize the efficiency of AI operations.</p></div><p><span class="TextRun SCXW164883129 BCX4" lang="EN-US" data-contrast="none"><span class="NormalTextRun SCXW164883129 BCX4">Staff/</span><span class="NormalTextRun SCXW164883129 BCX4">Principal<span class="Apple-converted-space"> </span></span><span class="NormalTextRun SCXW164883129 BCX4">ATE</span><span class="NormalTextRun SCXW164883129 BCX4"><span class="Apple-converted-space"> </span>Test Engineer</span></span><span class="EOP SCXW164883129 BCX4" data-ccp-props="{}"> </span></p> <p><strong>About The Team</strong></p> <p>We are open-minded, fast paced, problem solvers that value open dialogue and candor. Our passion is to challenge the status-quo and we embrace transformational thinking. Our response is never “no, but….” instead “yes, if….”. We are mindful of our personal and organizational blinders and try to build an environment where our team members are At Their Best.</p> <p><strong><span data-contrast="none">Location:</span></strong><span data-contrast="none"> Minimum of 3 days a week in the office in Torrance, CA. </span><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="none">About The Role</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="none">We are seeking a highly experienced Principal ATE Test Engineer to lead test development and production test strategy for a high-performance integrated voltage regulator (IVR) semiconductor product line targeting advanced AI and HPC power delivery applications.</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="none">This role is focused primarily on semiconductor test engineering, spanning DFT collaboration, characterization support, wafer probe, final test, hardware development, production ramp, and manufacturing optimization. The ideal candidate combines deep technical expertise in mixed-signal and power semiconductor test with strong leadership across silicon bring-up and high-volume manufacturing environments.</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="none">The candidate is expected to operate as a senior technical leader capable of driving test strategy independently across internal teams and external manufacturing partners. </span><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="none">What You Will Do</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Define overall manufacturing test strategy for IVR silicon across wafer probe and package final test</span> </li> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Develop production screening methodologies for:</span> </li> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Analog and mixed-signal circuits</span> </li> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Integrated ADCs and telemetry</span> </li> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Digital control and state machines</span> </li> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">PMBus/I2C interfaces</span> </li> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">OTP/eFuse programming</span> </li> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="none">Protection and fault-management circuitry</span> </li> <li data-leveltext="" data-font="Symbol" data-listid="1" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"