MatX designs next-generation AI processors aimed at outperforming Nvidia GPUs for large language model training and inference.
<p><strong>What MatX Is Building</strong></p> <p>MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability.</p> <h2><strong>About the Role</strong></h2> <p>We are looking for a skilled and hands-on Signal Integrity, Power Integrity, and Characterization (SIPI) Engineer to join our hardware team. In this role, you will own electrical characterization of high-speed SerDes interfaces and power delivery networks across our AI accelerator compute systems. You will build and scale test automation infrastructure capable of covering thousands of channels, while collaborating closely with SIPI engineers and board designers to influence and validate designs from early concept through production.</p> <h2><strong>What You'll Do</strong></h2> <p><strong>SerDes Characterization & Validation</strong></p> <ul> <li>Characterize high-speed SerDes interfaces (PCIe, Ethernet, custom protocols) including BER testing, eye diagram analysis, and PVT characterization</li> <li>Tune and optimize SerDes Tx and Rx equalization settings</li> <li>Perform channel characterization including insertion loss, return loss, and crosstalk measurements using VNA and time-domain reflectometry (TDR)</li> <li>Develop and execute correlation methodologies to align simulation predictions with measured results; drive feedback loops to improve modeling accuracy</li> </ul> <p><strong>Power Integrity Characterization</strong></p> <ul> <li>Measure and analyze high-current power rail transient noise and dynamic voltage droop on complex accelerator power delivery networks</li> <li>Characterize PDN impedance from board through package and silicon, and compare against target impedance specifications</li> <li>Identify PDN design weaknesses and collaborate with power delivery and board design teams to define and validate mitigation strategies</li> </ul> <p><strong>Test Automation & EDVT</strong></p> <ul> <li>Architect, develop, and maintain scalable test automation frameworks for Electrical Design Validation Testing (EDVT) across thousands of SerDes channels on multi-chip accelerator compute systems</li> <li>Integrate lab instruments (oscilloscopes, BERTs, VNAs, power analyzers) into automated test flows using Python or equivalent scripting environments</li> <li>Build robust data pipelines for test result collection, statistical analysis, and visualization to enable rapid triage and design decisions</li> </ul> <p><strong>Design Collaboration</strong></p> <ul> <li>Partner with SIPI engineers on optimization for advanced package designs, including die-to-die interconnects, bump arrays, and interposer structures</li> <li>Collaborate with board designers on PCB stackup definition, trace routing rules, via optimization, and decoupling strategies for high-speed accelerator boards</li> <li>Provide characterization data and actionable recommendations to influence layout guidelines, design rules, and future silicon/package revisions</li> </ul> <h2><strong>What We're Looking For</strong></h2> <p><strong>Experience & Education</strong></p> <ul> <li>5–10 years of industry experience in hardware characterization, SI/PI engineering</li> <li>Bachelor's degree or higher in Electrical Engineering; advanced degree a plus</li> <li>Deep understanding of high-speed SerDes architecture and operation — PHY layer fundamentals, equalization, jitter decomposition, and link margin analysis</li> <li>Strong grasp of transmission line theory — wave propagation, impedance matching, reflections, skin effect, and dielectric loss</li> <li>Solid understanding of PDN design principles — target impedance, resonance, bypass capacitor placement, and voltage regulator loop dynamics</li> <li>Hands-on proficiency with lab equipment</li> <li>Experience writing test automation scripts in Python (preferred)</li> </ul> <h2><strong>Bonus Points</strong></h2> <ul> <li>Background in AI accelerator or GPU system validation</li> <li>Familiarity with JEDEC or PCIe compliance testing methodologies</li> <li>Experience with statistical process control (SPC) or large-scale data analysis for silicon characterization</li> <li>Ability to do layout review for PCB, and advanced package design is a plus</li> </ul> <p><strong>Compensation</strong></p> <p>The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.</p> <ul> <li>Early Career - $120,000 - $250,000 + equity</li> <li>Mid Career - $175,000 - $362,500 + equity</li> <li>Senior Career - $250,000 - $475,000 + equity</li> </ul> <p><strong>What We Offer</strong></p> <ul> <li><strong>A Stake in our success </strong>A flexible cash equity compensation mix that fits your needs</li> <li><strong>Heath & Wellness </strong>Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)</li> <li><strong>Time To Recharge </strong>4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year</li> <li><strong>Support to Parents</strong> Up to 12 weeks of paid parental leave, regardless of your path to parenthood</li> <li><strong>Learning & Development </strong>$1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities</li> <li><strong>Team Connection</strong> Team Lunches, quarterly off-sites, and regular town halls</li> <li><strong>Financial Wellbeing </strong>401K and/or Roth IRA, with 5% company contribution, even if you don’t!</li> <li><strong>Flexible Spending Accounts</strong> Pre-tax spend accounts for medical, dental/vision, dependent care, parking, and transit expenses</li> <li><strong>Commute On Us</strong> For those commuting up to 1 hour, put your rideshare cost on our