Graphcore is an AI infrastructure and hardware company.
<p><strong>About Graphcore</strong></p> <p>At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.</p> <p><strong> </strong></p> <p><strong><span data-contrast="none">Job Summary</span></strong><strong><span data-contrast="none"> </span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI’s rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference.</span> <span data-contrast="auto">Reporting to the Director of Silicon Architecture, the SoC Architects are responsible for the design, specification, modelling and integration of sub-systems within complex, high performance and highly integrated silicon devices at the forefront of AI acceleration technology.</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">The role involves close collaboration with other groups, including architecture, silicon design, verification, hardware and software teams. </span><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">The Team</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">The Silicon Architecture Team sits within the COO group. The SoC architects are responsible for the architectural specification, integration, modelling, validation and evaluation of numerous critical sub-systems, including high-speed interfaces for our upcoming AI acceleration platforms.</span><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">Responsibilities and Duties</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="•" data-font="Calibri" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Calibri","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="0" data-aria-level="1"><span data-contrast="auto">Distilling product requirements and their effects on SoC/platform design trade-offs</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="Calibri" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Calibri","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Collaborating with processor, SoC and system architects to determine optimal solutions</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="Calibri" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Calibri","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Understanding of how to collaborate</span><span data-contrast="auto"> with silicon design, verification, and hardware engineers to </span><span data-contrast="auto">demonstrate awareness and options for implementation correctness</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="Calibri" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Calibri","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Evaluating potential hard and soft third-party IP and liaising with third party IP vendors</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="Calibri" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Calibri","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Design and specification of performant SoC sub-systems and their associated integrations</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="•" data-font="Calibri" data-listid="4" data-list-defn-props="{"335551671":0,"335552541":1,"335559685":720,"335559991":360,"469769226":"Calibri","469769242":[8226],"469777803":"left","469777804":"•","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Contribute to the silicon bring-up, characterisation and evaluation activities as required</span><span data-ccp-props="{}"> </span></li> </ul> <