Fractile is a UK AI hardware startup building next-generation inference chips and systems for frontier AI.
<p><span style="font-size: 12pt;"><strong>Bristol or London, 3 days in the office, 2 days WFH</strong></span></p> <p><span style="font-size: 12pt;">At Fractile, we’re building what we believe will be the world’s fastest AI inference chip from the ground up. We’re balanced across hardware and software engineering, and HW/SW co-design is real here. We move fast, and we help each other move fast. We care about each other, the software we ship, and the people who rely on it.</span></p> <p><span style="font-size: 12pt;">To validate behaviour, our functional simulator allows us to iterate at scale with real software before the hardware exists. It runs across multiple machines, supports large experiments, and helps verify the correctness of our low level firmware, runtime stack and compiler lowering.</span></p> <p><span style="font-size: 12pt;">You’ll be there for the first end-to-end runs against realistic device behaviour, the debugging sessions that unblock whole teams, and the moments where simulator fidelity turns into better software, better silicon decisions, and faster bring-up.</span></p> <h3><span style="font-size: 12pt;"><strong>What you’ll do</strong></span></h3> <ul> <li><span style="font-size: 12pt;">Build a functional simulator of Fractile’s AI accelerator hardware including a custom ISA</span></li> <li><span style="font-size: 12pt;">Implement the device models and behaviours that matter for software correctness: MMIO, interrupts, DMA, memory behaviour, concurrency, and error paths</span></li> <li><span style="font-size: 12pt;">Work closely with runtime, kernel, firmware and HW engineers to shape simulator interfaces</span></li> <li><span style="font-size: 12pt;">Make it usable at scale: tracing, determinism/reproducibility, CI integration, and containerised workflows</span></li> <li><span style="font-size: 12pt;">Collaborate daily with hardware, software, and ML engineers to validate assumptions and close gaps early</span></li> </ul> <h3><span style="font-size: 12pt;"><strong>What we’re looking for</strong></span></h3> <ul> <li><span style="font-size: 12pt;">Strong C and comfort working in large low-level codebases</span></li> <li><span style="font-size: 12pt;">Good intuition and knowledge of low-level hardware behaviour: registers/MMIO, interrupts, memory ordering, concurrency, and failure modes</span></li> <li><span style="font-size: 12pt;">You enjoy hard system-level problems, and you take them end-to-end until the results are measurable</span></li> <li><span style="font-size: 12pt;">Computer Science, Electronic Engineering, Maths, Physics, or related degree and 3+ years of industry experience</span></li> </ul> <h3><span style="font-size: 12pt;"><strong>Nice to have</strong></span></h3> <ul> <li><span style="font-size: 12pt;">You’ve built or extended hardware simulators or emulators.</span></li> <li><span style="font-size: 12pt;">SystemC experience</span></li> <li><span style="font-size: 12pt;">QEMU device model experience is ideal, even better in the TCG</span></li> <li><span style="font-size: 12pt;">Docker and orchestration tooling (Kubernetes)</span></li> <li><span style="font-size: 12pt;">Familiarity with RISC-V and x86 architectures</span></li> <li><span style="font-size: 12pt;">Python experience useful</span></li> </ul> <p><span style="font-size: 12pt;">If you want to build the simulator that makes rack-scale software real before rack-scale hardware exists, come build it together.</span></p> <p> </p>