Graphcore is an AI infrastructure and hardware company.
<p><strong>About Graphcore</strong><br>At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.<br><br></p> <p><strong><span data-contrast="none">Job Summary</span></strong><strong><span data-contrast="none"> </span></strong><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{}"> </span><span data-contrast="auto">We are looking for an experienced Silicon Test Engineer to join our Product Test and Diagnosis Department (PTD).</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="auto">This is a pivotal role and will involve building a team of engineers to develop System Level Test (SLT) capability within the company. Working closely with a cross-functional team you will implement SLT tests for a family of next generation AI Processors. </span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="none">The ideal candidate should have a focus on quality and demonstrate a good understanding of the importance of production test on the success of a product.</span><span data-ccp-props="{}"> </span></p> <p><span data-contrast="none">T</span><span data-contrast="auto">hey will have a proven Functional Test or ATE Test Engineering background, and will have a pragmatic, hands-on and flexible approach to a fast-changing environment.</span><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">The Team</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{}"> </span><span data-contrast="auto">The Product Test and Diagnostics team’s role is to detect and manage hardware defects that arise from the manufacture and use of our products. This covers chips, boards and finished systems and takes place both in the manufacturing sites and in the field. </span><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{}"> </span></p> <p><strong><span data-contrast="auto">Responsibilities and Duties</span></strong><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Managing a team of engineers to implement SLT test solutions for a multi-die AI Processor product</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Working with the Silicon, Test and DFT teams to define manufacturing test solutions</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Working with key industry leaders to develop an SLT system capable of meeting the products needs</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Understanding of top, and board level DFT strategies within a 3D, multi-die product</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Understanding of implementation details for an Incoming Quality Inspection (IQC) stage, and the inter-department complexities</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto">Defining test fixtures for SLT Test Solutions: Structural and functional test equipment, interface PCBs, sockets, cooling systems, etc</span><span data-ccp-props="{}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="6" data-list-defn-props="{"335552541":1,"335559685":360,"335559991":360,"469769226":"S