PowerLattice develops a power-delivery chiplet that reduces semiconductor power consumption by more than 50%.
About Us PowerLattice is a well-funded semiconductor startup backed by leading Silicon Valley venture capital firms. We are developing a groundbreaking chiplet solution for a fundamental shift in how high-performance chips are powered, paving the way for the next generation of AI and advanced computing. We are the first to offer a tiny device that can be integrated into a SoC package. About the Role We are seeking a technical expert to drive the design adoption of PowerLattice’s chiplet-based power delivery network (PDN) solution. PowerLattice is responsible for designing the chiplet for customers, which in turn saves power. This role sits at the intersection of deep technical expertise and customer engagement, serving as a critical bridge between our internal design teams and tier-one customers. The ideal candidate is highly organized, proactive, and articulate, with the technical credibility to partner directly with customer engineering teams working on the most advanced xPU SoCs in the industry. This role offers significant opportunity for impact, ownership, and growth, contributing directly to both customer product success and PowerLattice’s commercial momentum. This position is well suited for someone who thrives in a fast-paced startup environment, anticipates needs before they arise, and enjoys being a trusted technical advisor to customers and internal teams alike. Key Responsibilities - Enable customer to design GPU/CPU SoC power solution with PowerLattice’s chiplet - Assist customer’s PDN design optimization using PowerLattice’s design kit - Gather customer feedback and translate insights into improvements for customer enablement and product development - Assist customers through the full adoption lifecycle, from early modeling through physical design and system bring-up - Maintain strict confidentiality and handle sensitive technical information with discretion - Act as a primary technical point of contact for tier-one customers Minimum Qualifications This role is Hybrid requiring 3 days a week onsite at either our Chandler, AZ (Greater Phoenix) office, which is preferred, or Vancouver, WA (Greater Portland) office. While we are primarily seeking candidates in Chandler, remote flexibility may be considered for exceptional candidates based in Silicon Valley, CA - 8+ years of experience in power integrity and/or signal integrity for high-performance SoCs - Exceptional proficiency in power integrity or signal integrity tool chain and simulation flow - Hands-on experience extracting, building, and validating SoC package electrical models - Strong experience with package-level PI/SI, including substrates, interposers, and advanced packaging (2.5D / 3D) - Deep proficiency with PI/SI simulation tools and analysis workflows - Strong debugging skills across simulation and electrical testing environments - Excellent written and verbal communication skills, with the ability to engage directly with customer engineering teams - High level of professionalism, discretion, and sound technical judgment - Comfortable working independently and proactively solving problems Bonus Points - Working experience at major processor or ASIC companies in the related technical area - Proven experience as engineering or project lead in a related technical area - Hands-on experience with electrical test methodologies and instrumentation for power integrity or signal integrity - Experience in advanced package technologies, e.g. CoWoS, 2.5D Compensation & Benefits Anticipated annual base salary for Member of Technical Staff: $180,000 - $250,000 - Stock option grant - Comprehensive benefits package including health, dental, vision, and 401(k)