MatX designs next-generation AI processors aimed at outperforming Nvidia GPUs for large language model training and inference.
<p><strong>What MatX Is Building</strong></p> <p>MatX's mission is to make the world’s best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability.</p> <h2><strong>About the Role</strong></h2> <p>This is a senior-level, highly specialized engineering role focused on the design, qualification, and productization of next-generation optical interconnect technologies for AI scale-up and scale-out networks. The engineer owns the full lifecycle — from component characterization and link budget analysis to system-level bring-up and data center deployment — across the evolving spectrum of optical integration approaches: <strong>pluggables, NPO, and CPO</strong>.</p> <h2><strong>What You'll Do</strong></h2> <p><strong>Technology Evaluation & Qualification</strong></p> <ul> <li>Validate and productize high-speed copper and optical connectivity solutions for AI accelerator systems; own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers.<a href="https://job-boards.greenhouse.io/xai/jobs/5043570007"> </a></li> <li>Characterize and qualify optical modules across the integration spectrum — DSP Optics, LRO, LPO, NPO, and CPO — for 800G and 1.6T deployment in scale-up AI fabrics</li> <li>Perform link budget analysis and evaluate performance metrics including TDECQ, OMA, stressed receiver sensitivity, and associated diagnostics.</li> </ul> <p><strong>Component & System Engineering</strong></p> <ul> <li>Develop expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes, and characterization methodologies.<a href="https://job-boards.greenhouse.io/xai/jobs/5043570007"> </a></li> <li>Evaluate silicon photonics (SiPh) transceivers, VCSEL-based MMF links, and EML-based SMF solutions for scale-up fabric topologies</li> <li>Apply knowledge of thermal, mechanical, power, and signal integrity constraints in dense hardware environments.</li> </ul> <p><strong>Scale-Up Network Architecture</strong></p> <ul> <li>Define optical interconnect strategy for AI cluster topologies — rail-optimized, torus, dragonfly, and Clos — at XPU counts from 10K to 1M+</li> <li>Model and optimize end-to-end link budgets for 1.6T (200G/lane PAM4) across fiber types: SMF, MMF, MCF</li> <li>Engage with the transition from 1.6T to 3.2T (400G/lane) roadmaps and new form factors emerging with LPO and CPO.</li> </ul> <p><strong>Supply Chain & Vendor Management</strong></p> <ul> <li>Develop familiarity with subcomponent supply chains and global manufacturers, ODMs, and CMs.</li> <li>Manage technical relationships with optical module vendors (Coherent, II-VI/Coherent, Lumentum, Innolight, HG Genuine, Eoptolink) and silicon photonics suppliers</li> <li>Drive NPI (New Product Introduction) qualification plans, yield improvement, and reliability testing with manufacturing partners</li> </ul> <h2><strong>What We're Looking For</strong></h2> <p><strong>Experience & Education</strong></p> <ul> <li>BS/MS/PhD in Electrical Engineering, Optical Engineering, Physics, or Photonics</li> <li>7–12+ years in optical interconnect engineering, with at least 3 years focused on data center or AI fabric applications</li> <li>Hands-on experience qualifying 400G, 800G, or 1.6T optical modules in production environments</li> <li>Deep knowledge of PAM4 signal theory, SerDes architecture, and optical link physics at 200G per lane</li> <li>Proficiency in optical test equipment: BERT, OTDR, optical spectrum analyzers, sampling oscilloscopes (e.g., Keysight 86100), optical power meters, TDECQ testers</li> <li>Experience with OIF-CEI, IEEE 802.3dj electrical and optical compliance specs</li> <li>In-depth expertise in debugging and troubleshooting hardware; experience in the product development lifecycle.</li> <li>Understanding of fiber plant requirements: MPO/MTP connector, fiber cleanliness, insertion loss, PMD, and bend radius for high-density AI cluster cabling</li> <li>Experience with link budget modeling tools (MATLAB, Python-based photonic simulation, GNPY)</li> <li>Ability to collaborate with switch ASIC teams (SerDes architects), PCB/signal integrity engineers, thermal/mechanical engineers, and NOS/software teams</li> <li>Strong technical documentation and vendor communication skills</li> </ul> <h2><strong>Bonus Points</strong></h2> <p><strong>Background in AI accelerator or GPU system validationFamiliarity with JEDEC or PCIe compliance testing methodologiesExperience with statistical process control (SPC) or large-scale data analysis for silicon characterization</strong></p> <p><strong>Compensation</strong></p> <p>The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.</p> <ul> <li>Early Career - $120,000 - $250,000 + equity</li> <li>Mid Career - $175,000 - $362,500 + equity</li> <li>Senior Career - $250,000 - $475,000 + equity</li> </ul> <p><strong>What We Offer</strong></p> <ul> <li><strong>A Stake in our success </strong>A flexible cash equity compensation mix that fits your needs</li> <li><strong>Heath & Wellness </strong>Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)</li> <li><strong>Time To Recharge </strong>4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year</li> <li><strong>Support to Parents</strong> Up to 12 weeks of paid parental leave, regardless of your path to parenthood</li> <li><strong>Learning & Development </strong>$1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities</li> <li><strong>Team Connection</strong> Team Lunches, quarterly off-sites, and