AttoTude is a Menlo Park–based company developing ASIC over Dielectric interconnect technology for high-bandwidth, energy-efficient AI and hyperscale infrastructure connectivity.
<p><span data-contrast="auto">We are seeking a highly experienced Mixed-Signal IC Design Leader to join our growing team. In this role, you will be the technical lead in the design and development of cutting-edge mixed-signal ICs. You will be involved in the technical aspects of the IC design and development, from concept through to production. This is a hands-on technical position that requires in-depth technical expertise, and the ability to work in a team of highly experienced engineers to accomplishing the goals.</span><span data-ccp-props="{}"> </span></p> <p><span data-ccp-props="{"335551550":2,"335551620":2}"> </span></p> <p><strong><span data-contrast="none">Key Responsibilities:</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li style="line-height: 2;" data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Design and development of mixed-signal ICs for cutting edge AI and Cloud Computing systems </span></li> <li style="line-height: 2;" data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1">Ownership of the full design cycle, including architecture definition, block-level design, simulation, verification, layout and evaluation<span data-ccp-props="{"201341983":0,"335559740":256}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Drive high-speed interconnect design, including PAM4 SerDes >112Gbps in bulk CMOS and FinFET</span><span data-ccp-props="{"201341983":0,"335559740":256}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Design and optimization of Fractional-N synthesizers, multi-phase clock generation, and analog building blocks (e.g., Charge Pumps, Power Control)</span><span data-ccp-props="{"201341983":0,"335559740":256}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="auto">Implement and verify high-speed interconnects, Equalizers (CTLE/FFE/DFE, sample/hold), and other key components</span><span data-ccp-props="{"201341983":0,"335559740":256}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="auto">Collaborate with cross-functional teams to ensure timely project execution and design tape-outs</span><span data-ccp-props="{"201341983":0,"335559740":256}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="7" data-aria-level="1"><span data-contrast="auto">Stay updated with the latest trends and technologies in mixed-signal IC design and apply them to improve project outcomes</span><span data-ccp-props="{"201341983":0,"335559740":256}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="8" data-aria-level="1"><span data-contrast="auto">Occasional travel to the Bay Area (<10%) for remote position</span><span data-ccp-props="{"201341983":0,"335559740":256}"> </span></li> </ul> <p><span data-ccp-props="{"335551550":2,"335551620":2}"> </span></p> <p><strong><span data-contrast="none">Qualifications:</span></strong><span data-ccp-props="{}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">10+ years of hands-on experience in CMOS Mixed-Signal IC Design</span><span data-ccp-props="{"201341983":0,"335559740":256}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="3" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Proven expertise in designing high-speed interconnects, Fractional-N synthesizers, PAM4 SerDes (>112Gbps), Equalizers, and multi-phase clock generation</span><span data-ccp-props="{"201341983":0,"335559740":256}"> </span></li> </ul> <ul> <li data-leveltext=