Ethernovia develops high-performance Ethernet-based packet processors that serve as the data backbone for autonomous vehicles, robots and other edge AI machines.
<div class="content-intro"><p><strong>About Ethernovia, Inc.</strong></p> <p>Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018, the company’s breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing and AI-backed applications.<span class="Apple-converted-space"> </span></p> <p>Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. We are well-funded and backed by some of the worlds’ leading technology investors, having secured <strong>$154M</strong> ($90+M Series-B and $64M Series-A) in <strong>total funding</strong> to date:</p> <ul> <li><a href="https://www.businesswire.com/news/home/20260120549197/en/Ethernovia-Raises-Over-%2490-Million-Series-B-to-Scale-Leading-Edge-Autonomy-and-Physical-AI-Networking-Chips">Ethernovia Raises Over $90 Million Series B to Scale Leading-Edge Autonomy and Physical AI Networking Chips</a></li> <li><a href="https://www.businesswire.com/news/home/20230515005222/en/Ethernovia-Raises-64-Million-to-Accelerate-the-Revolution-of-Vehicle-Networks/">Ethernovia Raises $64 Million to Accelerate the Revolution of Vehicle Networks | Business Wire</a> <ul> <li>(financial backers include: Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon,<span class="Apple-converted-space"> Socratic Partners,</span> Conduit Capital, and CDIB-TEN Capital)</li> </ul> </li> </ul> <p><span data-teams="true">Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025.</span></p> <ul> <li>March 2026: <a href="https://www.businesswire.com/news/home/20260316729719/en/Ethernovia-Announces-HSB-Enabled-Networking-Board-for-NVIDIA-Holoscan-Platforms">Ethernovia Announces HSB-Enabled Networking Board for NVIDIA Holoscan Platforms</a></li> <li>January 2024: Our <a href="https://www.ethernovia.com/blog/ramin-named-motortrend-awards-winner/">CEO Ramin Shirani Named MotorTrend Software-Defined Vehicle Innovator Awards Winner (ethernovia.com)</a> </li> <li>September 2023: <a href="https://www.ethernovia.com/blog/continental-and-ethernovia-announce-partnership/">Continental and Ethernovia Announce Partnership to Develop Automotive Switch in 7nm - Ethernovia</a></li> <li><strong><a href="https://www.autoconnectedcar.com/2023/09/connected-car-news-helios-continental-ethernovia-avanci-bmw-mapbox-porsche-sema-honda-ultrasense-flex-logix-diodes-inc-garmin-toyota-caruso/#Continental_Ethernovia_for_SDVs">Connected Car News: Helios, Continental, Ethernovia, Avanci, BMW, Mapbox, Porsche, SEMA, Honda, UltraSense, Flex Logix, Diodes Inc., Garmin, Toyota & Caruso | auto connected car news</a></strong></li> </ul> <p>With talented employees on 4 continents, we have filed 50+ patents to date.</p> <p>Join Ethernovia’s team to make a lasting impact on the future of packet processor-centric networking solutions to support the real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots and intelligent machines. Come share in our success with pre-IPO shares, competitive compensation, and great benefits while growing your knowledge and career with world class talent. We are looking for talented engineers and leaders who have an entrepreneurial spirit and want to drive cutting edge designs from concept to silicon to the future of mobility.</p></div><p><strong>Lead Systems/DSP Engineer</strong></p> <p><strong>Summary:</strong></p> <p>We are seeking a seasoned DSP / System Architect to lead the design of <strong>next-generation high-speed (25G+) physical layer (PHY)</strong>. In this role, you will <strong>define and drive the end-to-end DSP architecture</strong>, from system-level modeling through silicon validation, enabling highly optimized, low-power, and high-performance transceiver implementations.</p> <p>This is a high-impact technical leadership role at the intersection of signal processing, mixed-signal design, and system architecture. You will work closely with cross-functional teams to translate advanced algorithms into robust, production-ready silicon.</p> <p><strong>Key Responsibilities</strong></p> <p>System Architecture & Technical Leadership</p> <ul> <li><strong>Define and own the DSP/system architecture for high-speed transceivers</strong>, balancing power, performance, and silicon area</li> <li>Drive key architectural decisions across DSP, analog front-end, and system partitioning</li> <li>Lead system-level trade-offs and provide technical direction across the organization</li> </ul> <p>Modeling & Algorithm Development</p> <ul> <li>Develop and maintain high-fidelity system models of complete transceivers using MATLAB, Simulink, Python, and/or C++</li> <li>Design, evaluate, and optimize advanced equalization techniques, including FFE, DFE and MLSD</li> <li>Architect robust Clock and Data Recovery (CDR) solutions with wide frequency acquisition range and very low phase noise</li> <li>Develop efficient and advance echo cancellation algorithms for full-duplex high-speed links optimizing for power and silicon area</li> <li>Design adaptive DSP algorithms with strong focus on rate of convergence, robustness, and implementation efficiency</li> <li>Develop channel model including nonlinear effects and complex noise sources</li> </ul> <p>System Integration & Cross-Functional Collaboration</p> <ul> <li>Translate system-level requirements into block-level specifications (AFE, ADC/DAC, PLL, DSP blocks, etc.)</li> <li>Collaborate closely with analog, RTL, and physical design teams to ensure accurate and efficient implementation</li> <li>Ensure alignment between algorithm models and hardware realization</li> </ul> <p>Silicon Validation & Product