MatX designs next-generation AI processors aimed at outperforming Nvidia GPUs for large language model training and inference.
<p><strong>What MatX Is Building</strong></p> <p>MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking Emulation engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies.</p> <p>We're hiring a Senior/Staff Emulation Engineer to build the infrastructure, flows, and debug methodology behind our advanced connectivity SoCs. The role sits in the Emulation team, but the impact is broader: you'll create reusable flows that span emulation, SoC simulation, firmware/software bring-up, and post-silicon validation.</p> <p>We're looking for a <strong>multi-disciplinary engineer</strong> with an out-of-the-box, can-do mindset — someone who sees a gap and builds the bridge, comfortable moving between RTL, software, tooling, system debug, and vendor flows. You don't need to be an expert in every area listed below. You do need a reuse-first mindset, strong software instincts, and the ability to learn quickly across boundaries.</p> <p><strong>What You'll Do Here</strong></p> <ul> <li>Define and execute emulation strategy and test plans for complex connectivity SoCs.</li> <li>Bring up and debug large-scale models on commercial emulation platforms such as Cadence Palladium, Zebu or Veloce.</li> <li>Integrate external components such as SpeedBridge and VirtualBridge adapters, Accelerated VIP, and memory models — for PCIe, HBM4, Ethernet, AXI/AMBA, JTAG, and (Q)SPI. And build custom transactors where needed. </li> <li>Develop HW/SW co-emulation and co-simulation flows using RTL, software/reference models (Rust, C/C++, SystemC), firmware, and software tests.</li> <li>Build reusable transactors, agents, stubs, bridges, checkers, and acceleration flows — including developing new transactors and agents from scratch when off-the-shelf options don't fit.</li> <li>Drive emulation speed-ups and resource utilization — compile-time reduction, partitioning, clocking strategy, regression scheduling, multi-user capacity, and waveform/trace management.</li> <li>Build automation for regression triage, debug, model usability, and engineering productivity.</li> <li>Go beyond prompting with AI — build practical LLM-based tooling for log analysis, waveform triage, debug assistance, and flow generation, including custom skills, agents, rules, and workflows that fit our engineering stack.</li> <li>Collaborate with architecture, RTL, DV, SoC, firmware, driver, kernel, validation, and EDA/vendor teams.</li> </ul> <p><strong>Who You Are</strong></p> <ul> <li>Strong hands-on experience with SoC emulation or system-level validation.</li> <li>Experience with at least one commercial emulation platform, such as Palladium.</li> <li>Working Verilog/SystemVerilog and waveform-debug skills — enough to develop a custom transactor or agent when needed (with or without AI assistance). Deep RTL design expertise is not required.</li> <li>Strong software and automation skills — Python plus one or more of C, C++, Rust, Tcl, or shell.</li> <li>Demonstrated ability to build tools and infrastructure, not just run existing flows.</li> <li>Strong system-level debug instincts spanning RTL, firmware, and software.</li> <li>Ability to work independently and across functional and team boundaries.</li> </ul> <p><strong>Bonus Points If You Have</strong></p> <ul> <li>UVM or hybrid SoC testbench development.</li> <li>Integrating cycle-accurate, software, or reference models into emulation/DV flows.</li> <li>Rust in verification or emulation flows (or strong interest in adopting it).</li> <li>Bazel or large-scale build/regression systems.</li> <li>Reusable stimulus across simulation, emulation, and post-silicon.</li> <li>AI/LLMs used to build real engineering tools — debug, triage, flow generation — beyond chat prompting.</li> <li>Connectivity SoCs, PCIe/CXL, Ethernet, DMA, HBM/memory subsystems, chiplets, or interconnect fabrics.</li> <li>Firmware or driver bring-up on emulation platforms.</li> <li>Scaling emulation or verification infrastructure across multiple projects or product lines.</li> </ul> <p><strong>Compensation</strong></p> <p>The US base salary for this full-time position is determined based on a variety of factors including role, experience, location, job related skills, and relevant education and training. Career length is only a guideline for compensation.</p> <ul> <li>Early Career - $120,000 - $275,000 + equity</li> <li>Mid Career - $175,000 - $450,000 + equity</li> <li>Senior Career - $275,000 - $600,000 + equity</li> </ul> <p><strong>What We Offer</strong></p> <ul> <li><strong>A Stake in our success </strong>A flexible cash equity compensation mix that fits your needs</li> <li><strong>Health & Wellness </strong>Company subsidized Health, Dental, Vision, and Life insurance; Pre-tax Health Savings Accounts with generous company contribution (even if you don’t)</li> <li><strong>Time To Recharge </strong>4 weeks paid time off (accrued), 12 company holidays, and 3 weeks remote/flexible work per year</li> <li><strong>Support to Parents</strong> Up to 12 weeks of paid parental leave, regardless of your path to parenthood</li> <li><strong>Learning & Development </strong>$1,500 yearly towards your professional development e.g. conferences, courses, and other learning opportunities</li> <li><strong>Team Connection</strong> Team Lunches, quarterly off-sites, and regular town halls</li> <li><strong>Financial Wellbeing </strong>401K and/or Roth IRA, with 5% company contribution, even if you don’t!</li> <li><strong>Flexible Spending Accounts</strong> Pre-tax s