Fractile is a UK AI hardware startup building next-generation inference chips and systems for frontier AI.
<div class="p-pdf_iframe__page" data-page-number="1"> <div class="textLayer"> <div class="p-workspace__primary_view_body"> <div class="p-message_pane p-message_pane--classic-nav p-message_pane--scrollbar-float-adjustment p-message_pane--with-bookmarks-bar" data-qa="message_pane"> <div id="message-list"> <div id="message-list" class="c-virtual_list c-virtual_list--scrollbar c-message_list c-scrollbar c-scrollbar--fade"> <div class="c-scrollbar__hider" data-qa="slack_kit_scrollbar"> <div class="c-scrollbar__child"> <div class="c-virtual_list__scroll_container" data-qa="slack_kit_list"> <div id="message-list_1759822621.811129" class="c-virtual_list__item" data-qa="virtual-list-item" data-item-key="1759822621.811129"> <div class="c-message_kit__background c-message_kit__background--hovered p-message_pane_message__message c-message_kit__message" data-qa="message_container" data-qa-unprocessed="false" data-qa-placeholder="false"> <div class="c-message_kit__hover c-message_kit__hover--hovered" data-qa-hover="true"> <div class="c-message_kit__actions c-message_kit__actions--default"> <div class="c-message_kit__gutter"> <div class="c-message_kit__gutter__right" data-qa="message_content"> <div class="c-message_kit__blocks c-message_kit__blocks--rich_text"> <div class="c-message__message_blocks c-message__message_blocks--rich_text" data-qa="message-text"> <div class="p-block_kit_renderer" data-qa="block-kit-renderer"> <div class="p-block_kit_renderer__block_wrapper p-block_kit_renderer__block_wrapper--first"> <div class="p-rich_text_block"> <div class="p-rich_text_section"> <h2><strong>About Fractile</strong></h2> <p>Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.</p> <p>The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems. </p> <h2><strong>The Role</strong></h2> <p>This role will design, implement, and support production-ready board/PCBA test solutions for a high-volume board integrating multiple AI accelerator chips, high-current power delivery, embedded control, and PCIe Gen6 interconnect. This is a hands-on individual contributor role focused on executing the board test strategy defined by the Board Test Engineering Lead and delivering robust, repeatable tests for offshore manufacturing.We are seeking an experienced <span class="il">DRAM</span> Product Engineer to develop advanced test methodologies and diagnostic techniques for next-generation memory systems.</p> <p>This role focuses on understanding <span class="il">DRAM</span> behavior across logical, architectural, and physical domains, using simulation, statistical analysis, and mathematical modeling to investigate failure mechanisms, characterize performance margins, define test techniques and improve reliability and yield. The successful candidate will combine deep knowledge of <span class="il">DRAM</span> architecture and circuit behavior with strong analytical and problem-solving skills, working closely with design, architecture, and manufacturing teams to drive memory test innovation and product quality.</p> <ul> <li>Develop and execute test strategies for <span class="il">DRAM</span> devices and their interconnects, covering functional, timing, signal integrity, and reliability failure modes.</li> <li>Diagnose complex <span class="il">DRAM</span> issues across logical, architectural, and physical domains, including cell behavior, addressing, timing margins, and interface interactions.</li> <li>Build, modify, and maintain simulation models to study <span class="il">DRAM</span> behavior, interfaces, and test scenarios at multiple abstraction levels.</li> <li>Use simulation tools to explore corner cases, stress conditions, and failure mechanisms prior to and alongside silicon testing.</li> <li>Transform and correlate data between logical representations (addresses, transactions, algorithms) and physical implementations (cells, banks, rows/columns, wires, timing paths).</li> <li>Analyze <span class="il">DRAM</span> behavior with a deep understanding of circuit operation, including variability, noise, leakage, and process effects.</li> <li>Apply statistical methods to large test datasets to identify trends, characterize distributions, isolate root causes, and support yield and reliability conclusions.</li> <li>Use mathematical models to describe, predict, and explore <span class="il">DRAM</span> test behavior, limitations, and tradeoffs.</li> <li>Collaborate with design, architecture, and manufacturing teams to feed diagnostic insights back into design and test improvements.</li> </ul> <h2><strong>About you</strong></h2> <p><strong>Required Skills and Experience</strong></p> <ul> <li>BS or MS in Electronics and Electrical Engineering or related field.</li> <li>Strong background in <span class="il">DRAM</span> architecture, operation, and interfaces.</li> <li>Solid understanding of <span class="il">DRAM</span> failure modes, and associated test a