Graphcore is an AI infrastructure and hardware company.
<h2><strong>About Graphcore</strong></h2> <p>At Graphcore, we’re building the future of AI compute.</p> <p>We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.<br><br>As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem. To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.<br><br>We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence.</p> <p><strong><span data-contrast="auto">The Person</span></strong><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></p> <p><span data-contrast="auto">Graphcore’s </span><span data-contrast="auto">experienced, skilled, and motivated engineering team is heavily involved in shaping the future of AI.</span> <span data-contrast="none">A successful candidate </span><span data-contrast="none">will exhibit exceptional knowledge in Design for Testability (DFT) and </span><span data-contrast="none">will have a </span><span data-contrast="none">strong technical background and experience in DFT methodologies, complemented by a robust, self-motivated work ethic. The ideal candidate should also</span><span data-contrast="none"> have a focus on quality</span><span data-contrast="none"> and demonstrate</span><span data-contrast="none"> a good understanding of the importance of production test on the success of a product. Some hands-on experience in one or more of the following areas is essential: RTL design, simulations and debugging, synthesis, STA. </span><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></p> <p><strong><span data-contrast="none">The Role:</span></strong><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></p> <p><span data-contrast="none">We are expanding and looking for an experienced DFT engineers to join the Silicon team. As a part of our team, you will have the opportunity to work on next-generation AI designs targeted for data centers applications.</span><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></p> <p><strong><span data-contrast="none">Responsibilities:</span></strong><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></p> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Keep up with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies</span><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="2" data-aria-level="1"><span data-contrast="auto">Work closely with design, verification, physical design and product engineering teams to integrate DFT requirements into the overall design process</span><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="3" data-aria-level="1"><span data-contrast="auto">Define and implement DFT architecture and features for next-generation AI designs and support their verification effort</span><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="4" data-aria-level="1"><span data-contrast="auto">Develop efficient DFT flows and methodology compatible with silicon design flows</span><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="5" data-aria-level="1"><span data-contrast="none">Work with 3rd party IPs to integrate the provided design into the DFT infrastructure</span><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"multilevel"}" data-aria-posinset="6" data-aria-level="1"><span data-contrast="none">Generate structural test vectors, analyze and improve test coverage</span><span data-ccp-props="{"201341983":0,"335551550":6,"335551620":6,"335559739":0,"335559740":240}"> </span></li> </ul> <ul> <li data-leveltext="" data-font="Symbol" d