Staff Engineer, CPU Core Verification
at Tenstorrent
- Seniority
- Staff Principal
- Work model
- Hybrid
- Location
- Bengaluru, Karnataka, India
- Posted
- 13d ago
c++
at Tenstorrent
<div class="content-intro"><p>Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.</p></div><p>At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon.</p> <p>This role is<strong> </strong>hybrid, based out of Bangalore, India.</p> <p>We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.</p> <p> </p> <p><strong>Who You Are</strong></p> <ul> <li>You bring 8+ years in CPU verification or closely related digital design.</li> <li>You know high‑performance out‑of‑order CPU microarchitecture in depth.</li> <li>You work comfortably with RTL, waveforms, logs, and complex debug scenarios.</li> <li>You communicate clearly across design, DV, emulation, and post‑silicon teams.</li> </ul> <p> </p> <p><strong>What We Need</strong></p> <ul> <li>Plan and drive functional verification for CPU core features and complex microarchitectural scenarios.</li> <li>Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components.</li> <li>Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently.</li> <li>Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure.</li> <li>Collaborate with design, validation, and test teams to support bring-up and delivery of robust CPU cores and clusters.</li> </ul> <p> </p> <p><strong>What You Will Learn</strong></p> <ul> <li>How Tenstorrent designs and validates high‑performance RISC‑V CPU cores and clusters.</li> <li>Techniques for spanning pre‑silicon, emulation, and post‑silicon verification with shared stimulus.</li> <li>Ways to scale coverage, debug, and infrastructure across multiple CPU programs.</li> <li>How open hardware and software fit into Tenstorrent’s broader compute roadmap.</li> </ul> <p> </p> <p><em>Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.</em></p><div class="content-conclusion"><p><em>This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.</em></p></div>