PCIe Post-Silicon Validation Engineer
at Astera Labs
- Location
- Tel Aviv-Yafo, Tel Aviv District, Israel
- Posted
- 5d ago
python
at Astera Labs
<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p> </p> <div class="x_elementToProof" data-olk-copy-source="MessageBody">We are looking for a <strong>PCIe Post-Silicon Validation Engineer</strong> with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.</div> <div class="x_elementToProof"><strong>Key Responsibilities</strong></div> <ul data-spread="false"> <li> <div>Perform hands-on <strong>PCIe post-silicon validation</strong></div> </li> <li>Debug PCIe link issues including <strong>link training, LTSSM, equalization, recovery, resets, and link stability</strong>.</li> <li>Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.</li> <li>Drive complex issues from initial failure through <strong>root-cause analysis and final resolution</strong>.</li> <li>Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.</li> <li>Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.</li> <li>Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.</li> <li> <div>Develop automation to improve validation coverage, debug efficiency, and regression testing.</div> </li> </ul> <div class="x_elementToProof"><strong>Required Qualifications</strong></div> <ul data-spread="false"> <li>BS/MS in <strong>Electrical Engineering, Computer Engineering, Computer Science</strong>, or equivalent experience.</li> <li><strong>5+ years of engineering experience</strong> in silicon validation, post-silicon debug, or high-speed interface development.</li> <li>Strong hands-on knowledge of <strong>PCIe architecture and protocol</strong>.</li> <li> <div>Experience working with PCIe analyzers, state traces, registers, logs, eye diagrams, and/or signal-integrity measurements.</div> </li> <li>Strong problem-solving skills and ability to independently drive issues to root cause.</li> <li>Experience working across <strong>hardware, firmware, and software</strong> boundaries.</li> <li> <div>Good scripting/programming skills, preferably <strong>Python </strong></div> </li> <li>Good Linux knowledge and experience with Linux PCIe debug tools.</li> <li>Strong communication and collaboration skills.</li> </ul> <div class="x_elementToProof"><strong>Preferred Qualifications</strong></div> <ul data-spread="false"> <li> <div class="x_elementToProof">Experience with <strong>PCIe Gen4/Gen5/Gen6/Gen7</strong></div> </li> <li>Hands-on experience with PCIe PHY, SerDes, equalization, lane margining, or signal integrity.</li> <li>Experience with PCIe compliance and interoperability testing.</li> <li>Experience debugging intermittent, marginal, thermal-sensitive, or corner-case PCIe failures.</li> <li> <div class="x_elementToProof">Experience with PCIe switches, or networking/accelerator platforms.</div> </li> <li> <div>Practical experience using AI/ML tools for engineering debug and automation.</div> </li> </ul> <p> </p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>