Firmware/Software Tech Lead

About this role

<div class="content-intro"><p><span data-teams="true">Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at <a id="menurhut" class="fui-Link ___1q1shib f2hkw1w f3rmtva f1ewtqcl fyind8e f1k6fduh f1w7gpdv fk6fouc fjoy568 figsok6 f1s184ao f1mk8lai fnbmjn9 f1o700av f13mvf36 f1cmlufx f9n3di6 f1ids18y f1tx3yz7 f1deo86v f1eh06m1 f1iescvh fhgqx19 f1olyrje f1p93eir f1nev41a f1h8hb77 f1lqvz6u f10aw75t fsle3fq f17ae5zn" href="http://www.asteralabs.com/" target="_blank">www.asteralabs.com</a>.</span></p></div><p>&nbsp;</p> <p class="p8i6j01 paragraph">Astera Labs is hiring a <strong>Tech Lead Design Engineer</strong> to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.</p> <p class="p8i6j01 paragraph">This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.</p> <h3 class="_9k2iva0 p8i6j0c _1ibi0s314 heading3 _9k2iva1">Key Responsibilities</h3> <ul class="p8i6j07 p8i6j02"> <li class="p8i6j0a"><strong>RTL Design &amp; Implementation</strong> <ul class="p8i6j08 p8i6j02"> <li class="p8i6j0a">Own RTL design for assigned blocks from microarchitecture through synthesis sign-off</li> <li class="p8i6j0a">Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA</li> <li class="p8i6j0a">Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality</li> </ul> </li> <li class="p8i6j0a"><strong>Cross-Functional Execution</strong> <ul class="p8i6j08 p8i6j02"> <li class="p8i6j0a">Partner with architecture to translate specifications into implementation-ready microarchitecture</li> <li class="p8i6j0a">Collaborate with verification on testplans, coverage closure, and bug triage</li> <li class="p8i6j0a">Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure</li> </ul> </li> <li class="p8i6j0a"><strong>Technical Leadership &amp; Quality</strong> <ul class="p8i6j08 p8i6j02"> <li class="p8i6j0a">Mentor junior engineers and contribute to design methodology, scripts, and best practices</li> <li class="p8i6j0a">Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments</li> <li class="p8i6j0a">Drive structured, data-driven design decisions in support of aggressive tapeout schedules</li> </ul> </li> </ul> <h3 class="_9k2iva0 p8i6j0c _1ibi0s314 heading3 _9k2iva1">Basic Qualifications</h3> <ul class="p8i6j07 p8i6j02"> <li class="p8i6j0a">Bachelor's degree in Electrical Engineering, Computer Engineering, or related field</li> <li class="p8i6j0a">5+ years of digital design experience, including at least one full chip from spec to tapeout</li> <li class="p8i6j0a">Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows</li> <li class="p8i6j0a">Hands-on experience with timing closure, CDC, lint, and low-power design techniques</li> <li class="p8i6j0a">Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration</li> </ul> <h3 class="_9k2iva0 p8i6j0c _1ibi0s314 heading3 _9k2iva1">Preferred Qualifications</h3> <ul class="p8i6j07 p8i6j02"> <li class="p8i6j0a">MS or PhD in Electrical Engineering or Computer Engineering</li> <li class="p8i6j0a">Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs</li> <li class="p8i6j0a">Familiarity with formal verification, emulation, or assertion-based methodologies</li> <li class="p8i6j0a">Background in advanced process nodes (7nm, 5nm, or below)</li> <li class="p8i6j0a">Strong debug skills across pre-silicon and post-silicon environments</li> </ul> <p class="p8i6j01 paragraph">Salary range is $160,000 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.</p> <p>&nbsp;</p><div class="content-conclusion"><p>We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.</p></div>