ASIC Design Engineer – DSP / Analog / SerDes

About the company

Celero Communications develops advanced optical networking chips designed to connect artificial-intelligence data centers over long distances with higher speed and lower power consumption.

About this role

<p><strong>ASIC Design Engineer – DSP / Analog / SerDes</strong></p> <p>Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems.</p> <p>Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. The ideal candidate will have strong digital ASIC design expertise combined with hands-on experience in DSP, Analog, and/or SerDes technologies.</p> <p><strong>What You Will Do</strong><br>• Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.<br>• Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.<br>• Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs.<br>• Participate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems.<br>• Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities.<br>• Optimize designs for performance, power, and area (PPA).<br>• Perform RTL simulation and debugging to ensure design functionality and performance.<br>• Contribute to block-level and top-level integration, verification, and silicon bring-up.<br>• Participate in architecture and design reviews and provide technical guidance to other engineers.<br>• Collaborate with cross-functional teams to troubleshoot complex design and system-level issues.<br>• Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.<br>• Contribute to ASIC development from architecture and RTL through tapeout and silicon validation.</p> <p><strong>What You Will Bring</strong><br>• Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related field.<br>• 5+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.<br>• Strong proficiency in Verilog and/or SystemVerilog.<br>• Strong understanding of digital design principles, RTL design, and ASIC development methodologies.<br>• Hands-on experience with ASIC design flows and industry-standard EDA tools.<br>•<strong> Strong knowledge of one or more of the following areas:&nbsp;</strong><br><strong>- Digital Signal Processing (DSP)</strong><br><strong>- High-speed SerDes</strong><br><strong>- Analog/Mixed-Signal ICs</strong><br><strong>- Digital communications</strong><br><strong>- Optical communications</strong><br>• Experience working with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or other high-speed communication technologies.<br>• Understanding of SerDes architectures and high-speed interfaces, including TX/RX datapaths, equalization, clocking, and related mixed-signal interfaces.<br>• Experience collaborating with Analog and Mixed-Signal design teams and understanding the interaction between digital, analog, and SerDes blocks.<br>• Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.<br>• Familiarity with verification methodologies such as UVM and/or formal verification.<br>• Knowledge of low-power design techniques and PPA optimization.<br>• Strong analytical and problem-solving skills.<br>• Excellent communication and teamwork skills with the ability to work effectively in a fast-paced startup environment.</p> <p><strong>Preferred Qualifications</strong><br>• Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.<br>• Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.<br>• Experience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry.<br>• Experience working with advanced semiconductor process technologies.<br>• Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.<br>• Experience with MATLAB, Python, Tcl, or other modeling and automation tools.<br>• Understanding of optical communication standards and high-speed networking protocols.<br>• Experience working in a startup or fast-paced semiconductor development environment.</p> <p><strong>Why Join Celero?</strong><br>At Celero, you will have the opportunity to work on challenging, high-performance semiconductor technologies at the intersection of AI infrastructure, optical communications, DSP, SerDes, and mixed-signal design. You will work closely with experienced engineers across multiple disciplines and have the opportunity to make significant contributions to products from architecture through silicon.</p>